Various types of 2D/2D prototype devices based on graphene (G) and boron nitride nanosheets (BNNS) were fabricated to study the charge tunneling phenomenon pertinent to vertical transistors for digital and high frequency electronics. Specifically, G/BNNS/metal, G/SiO, and G/BNNS/SiO heterostructures were investigated under direct current (DC-bias) conditions at room temperature. Bilayer graphene and BNNS were grown separately and transferred subsequently onto the substrates to fabricate 2D device architectures. High-resolution transmission electron microscopy confirmed the bilayer graphene structure and few layer BNNS sheets having a hexagonal B-N lattice. The current vs voltage I(V) data for the G/BNNS/Metal devices show Schottky barrier characteristics with very low forward voltage drop, Fowler-Nordheim behavior, and 10 Ω/sq. sheet resistance. This result is ascribed to the combination of fast electron transport within graphene grains and out-of-plane tunneling in BNNS that circumvents grain boundary resistance. A theoretical model based on electron tunneling is used to qualitatively describe the behavior of the 2D G/BNNS/metal devices.