The paper deals with design and transformation methodology of autosynchronous state machines. The result is the design methodology for autosynchronous state machines with one-hot and Gray encodings. On the basis of their simulation models the timing parameters are defined and conditions for the correct behavior are pointed out. In order to simplify the design of these state machines, the transformation methodology of synchronous state machine in VHDL at RTL level to autosynchronous state machine is designed. These transformed state machines are compared in their chip area, power consumption and timing.